Digital computer gating device



Nov. 3, 1964 o D PARHAM 3,155,846

DIGITAL COMPUTER GATING DEVICE Filed April 19 1962 4 Sheets-Sheet 1 Nov. 3, 1964 o D PARHAM 3,155,846

DIGITAL COMPUTER GATING DEVICE Nov. 3, 1964 o D PARHAM 3,155,846

DIGITAL COMPUTER EATING DEVICE Filed April 19, 1962 4 sheets-sheet s y QM QQ( 9W Nov. 3, 1964 o D PARHAM 3,155,846

DIGITAL' COMPUTER GATING DEVICE Filed April 19, 1962 4 Sheets-Sheet 4 Var/rai United States Patent O FPice 3,155,846 DHGETAL @h/WEITER GA'EHNG DEVICE 0 D 1arhani, Downey, Calif., assigner to Hughes Aircraft Company, Cuiver City, Calif., a corporation of Deiaware Fitted Apr. i9, i962, Ser. No. @8,688 7 Claims. (Ci. Supl-88.5)

This invention relates to digital computer gating devices hereafter designated as or and Lnor gates and, more particularly, to digital computer gating apparatus capable of providing extremely fast logic rates.

In the mechanization of apparatus for performing various computational problems, speed requirements have often necessitated the use or' a parailel system as distinguished from a serial system. Extremely fast serial systems or subsystems made feasible by the gating devices of the present invention will thus minimize the need for a parallel system.

lt is therefore an object of the present invention to provide improved digital computer gating apparatus.

Another object of the present invention is to provide digital computer gating apparatus capable of providing extremely fast logic rates.

Still another object of the present invention is to pro- I vide or and nor gating devices capable of operating at clock rates in excess of 100 megacycles.

A further object of the present invention is to provide or and nor digital computer gating devices which exploit the characteristics of tunnel and backward diodes.

A still further object of the present invention is to provide nor and or digital computer gating devices which place a substantially constant current drain on the associated direct current power sources.

In accordance with the present invention, current flow through first and second serially connected tunnel diodes is controlled in a manner to produce changes in potential level at the junction therebetween which constitutes the output of the device. More particularly, circuitry instrumenting or or nor logic is employed to divert current from at least one of the tunnel diodes thereby to cause a switch in the mode of current iiow therethrough. That is, the same value of current through a tunnel diode corresponds to two different voltage drops thereacross, the particular one depending upon whether or not the peak current, ip, of the particular tunnel diode had been exceeded. Further, it has been determined that switching between modes of current flow through a tunnel diode takes place in a period of time less than 0.3 nanosecond thus making it possible to achieve extremely fast switching. Lastly, a sinusoidal clock signal which may have a frequency as high as 160 megacycles or more is employed to periodically clear the gating devices of the present invention.

The above-mentioned and other features and objects of this invention and the manner or" obtaining them will become more apparent by reference to the following description taken in conjunction with the accompanying drawings wherein:

FIG. l shows a preferred embodiment of a nor gate in accordance with the present invention adapted to provide positive current output;

FIG. 2 shows a preferred embodiment of a nor gate in accordance with the present invention adapted to provide negative current output;

FlG shows a preferred embodiment of an or gate in accordance with the present invention which is adapted to provide positive current output; t

FIG. 4 shows a preferred embodiment of an or gate in accordance with the present invention adapted to provide negative current output;

FIG. 5 illustrates waveforms of the clock together with iiatented Nov.r 3, i964 waveforms avaiiable at the respective input and output of the gating device of FIG. 1 when operating at a clock rate of 40 megacycles; and

FEGS. 6 and 7 illustrate typical current-voltage characteristics of tunnelr and backward diodes of the type employed inthe apparatus of FlGS. l-4.

In the following description of the present invention, reference is made to tunnel and backward diodes. Referring to FIGS. 6 and 7 of the drawings, there is illustrated current-voltage characteristics of tunnel and backward diodes, respectively, together with the manner in which they are designated in the remainder of the drawings. Referring now to FIG. .6, there is illustrated a typical current vs. voltage characteristic 16 of the tunnel diode wherein current ilow is indicated along the abscissa and voltage-drop across the diode is indicated along the ordinate. ln addition, a symbol 11 is employed to designate a tunnel diode. Symbol 11 constitutes a square 12 enclosing a V 13 which extends from one side of the square 12 to the mid-point of the opposite side thereof. Cathode lead 14 connects to the vertex of the V 13 and an anode lead 1S connects to the mid-point of the side of the square 12 opposite the vertex of the V 13. Normal current flow through the tunnel diode il is considered to be from anode l5 to cathode 14 and is represented by positive values of current llow of the characteristic 10. Current tiow through the tunnel diode l1 in a backward direction is considered to be current flow from the cathode 14 to the anode 1S. Under these circumstances the cathode 14 is necessarily positive relative to the anode i5. Current flowof this type is represented by the negative values of current flow of the characteristic 10. in particular, current flow in a normal direction through a tunnel diode increases in proportion to the voltage drop thereacross until a peak current, Ip, is reached. Operation of a tunnel diode at currents less than II, is designated as operation in the non-switched mode and operation at currents in excess of lp is designated as operation in the switched inode. Further, increasing the current through a tunnel diode is designated as setting the tunnel diode, i.e., changing the mode of operation from the nonswitched to the switched mode. Lastly, the voltage drop across the tunnel diode corresponding to the peak current, Ip, is referred to as the peak voltage, Vp. After the peak current, Ip, is reached, the voltage drop continues to increase with a decrease in current until a null is reached designated by point l on the characteristic it?. This null at point 17 is generally referred to as the valley voltage, Vv, of the tunnel diode and occurs, for example, at a voltage of the order of 350 millivolts. Increases in voltage across a tunnel diode in excess of the valley voltage, Vv, or the tunnel diode and occurs, for With regard to current flow through a tunnel diode in a backward direction, current ow in general increases in proportion to the voltage drop thereacross with a current ow equal to twice the peak current, Ip, of the tunnel diode corresponding generally to a voltage drop thereacross equal to 0.1 the valley voltage of the tunnel diode. For the purposes of the present invention, any device having a current-voltage characteristic that is of the same type as the current-voltage characteristic 1t) is considered to be the equivalent Vof a tunnel diode and, as such, is within the scope of the teachings of this speciiication.

Referring now to FIG. 7 of the drawings, symbol 20 is employed to designate a backward diode and constitutes a short transverse line disposed across a lead together with a V having the vertex thereof at the intersection. Normal current iiow through a backward diode is considered to be in the direction indicated by the V (When considered as an arrow) and is represented by the portion of a characteristic 22 which corresponds to positive current flow.

arrests y Backward current flow through a backward diode constitutes current flow therethrough in the opposite direction and corresponds to the portion of characteristic 22 where the current flow is negative. in general, when the current flow through the backward diode is in the normal direction, the potential drop thereacross increases proportionately to the current flow therethrough as illu"- trated by the upper portion characteristic 22, as viewed in the drawing. In the backward direction, however, there is a slight negative current in regions where the backward voltage drop thereacross is small. This current, however, decreases to zero and remains at Zero until voltage drops of the order of 0.4 volt are reached. After this point, current ilow rapidly increases with a maximum voltage drop thereacross of the order of 0.5 volt. For this reason, maximum backward voltage normally used across a backward diode having a characteristic of the same type as characteristic 22 is generally of the order of 0.3 volt. Although backward diodes are described in the gating networks of the following embodiments, it is only necessary that this type of diode be used when extremely fast speeds of operation are desired.

Referring now to FIG. l of the drawings, there is shown a preferred embodiment of a nor gate in accordance with the present invention adapted to generate a binary l gating signal or positive polarity at the output thereof. In particular, tunnel diodes 3d, 32 are serially connected from a junction 33 to a junction and are poled in a manner to mlow normal current tlow pr ceeding from junction 33 to junction 34. A junction 35 constitutes the common junction intermediate the tunnel diodes 30, 32. Also, in accordance with the present in` vention, tunnel diode is of a type having a peak current, Ip, of 2 milliamperes and tunnel diode 32 is or" a type which has a peak current, In, which is no less than the peak current of diode 3i) and is preferably of the order of 5 milliamperes, Tunnel diodes 3), 32 are presently available commercially as 1N2969 and iN294l, respectively. The junction 34 is maintained at a ixed directcurrent potential of the order of 150 millivolts relative to ground by means of a connection therefrom to a power supply 37 which is, in turn, referenced to ground. The junction 33, on the other hand, is returned to ground through a backward diode 33, which diode 38 is poled in a direction to allow normal current iiow from junction 33 towards ground. The purpose or" backward diode 3S is to prevent the potential difference between junctions 33, 34 from exceeding 400 millivolts so that tunnel diodes 3d, 32 cannot be switched simultaneously and, in addition, prevents the tunnel diodes 30, 32 from operating too far into the region where the voltage thereacross exceeds the valley voitage, Vv, where the recovery time of the respective diode is slow.

An output from the disclosed gating apparatus is provided by appropriate connections from the junction 3S intermediate the tunnel diodes 36, 32 to output terminals 4G. The output signal produced is in the nature of a current or no current. Inputs to the device are provided by input terminals 41, 42, 43. The input terminais di, 4Z, d3 are connected through backward diodes 4' 5, 46, respectively, to a common junction 47, which ,i nction 47 is, in turn, connected through a backward diode 48 to the junction 35 and, in addition, is returned to ground through a backward diode 5t?. The backward diodes 44, 45, 46 are poled in a manner to allow normal current low towards the input terminals di, ft2, d3, respectively; the backward diode is polcd in a manner to allow normal current liow towards the junction and the backward diode St) is polcd in a manner to allow normal current how towards ground. Next, a source of substantially constant current tlow towards the junction 47 is provided by a resistor 52 connected from the junction 47 to the positive terminal of a battery Sli, the remaining terminal ot which is referenced to ground. The resistor 52 has a resistance of the order of 8400 ohms,

and the battery S4 provides a potential of the order of +5 volts whereby a substantially constant current of the order of 0.6 milliampere tiows through the resistor 52 towards the junction 47. Further, a resistor 55 is connected from the junction 35 to the positive terminal of the battery 5ft and has resistance of the order of 1860 ohms whereby a substantially constant current of the order of 2.7 milliarnperes hows toward the junction 3S. Further, a resistor 56 is connected from the junction 33 to the positive terminal of battery S4 and has a resistance of the order of i860 ohms whereby a substantially constant current of the order of 2.7 milliamperes ilows toward the junction 33.

ri`he apparatus of the present invention is adapted, but not restricted, to function in response to a sinusoidal clock signal which is applied to a terminal 60. Terminal 66 is connected through a resistor dividing network to ground constituting resistors 61, 62, which resistors are serially connected in the order named from terminal 60 to ground. Resistor 61 has a resistance of the order of 500 ohms and resistor 62 has a resistance of the order of 56 ohms thereby to provide a voltage at the common junction therebetween which is approximately 10% of the voltage applied to the clock input terminal 60. The purpose for this is to allow the use of a larger amplitude clock signal so as to minimize any effects due to variations in amplitude. The voltage appearing at the junction between resistors 61, 62 is coupled through a capacitor 64 to the junction 33 at one extremity of the tunnel diode 30. The capacitance of capacitor 64 is not critical and may, for example, be of the order of 120 micromicrofarads.

In the operation of the apparatus of FIG. 1, signals representative of either binary l or binary 0 are applied to the input terminals 41, 42, 43. For this pun pose, the potential level of binary 0 is deined at +100 millivolts and corresponds to Zero current How. The potential level of binary 1, on the other hand, is defined as -200 millivolts and corresponds to a current ilow of the order of 0.6 milliampere towards the input terminals 41, 42, or #i3 through the backward diodes 44, 45 or 46, respectively. In addition, a sinusoidal clock signal har/ng a waveform 70, FSG. 5, is applied to the clock input terminal 60. The frequency of the clock signal determines, of course, the speed at which the apparatus functions. The frequency of this clock signal may be as low as one megacycle or less and as high as several hundred megacycles depending on the nature of the computer system. In the present case, the waveform 70 having a clock frequency of 40 megacycles, together with associated input and output waveforms corresponding to this frequency, are illustrated in FIG. 5. In the following description, the positive alternation of the clock signal 70 is referred to as the e alternation and the negative alternation is referred to as the alternation. Lastly, as will be evident from the following description, the 'waveform of the clock signal, although preferably' sinusoidal, may assume other periodic contigurations.

The apparatus of the present invention generates an output signal having one of two different potential levels thereby to produce potential levels representative of either binary l or binary 0 at the output terminals 40. Unlike the input terminals 4l, 42, 43, a potential evel of millivolts at the output terminals 40 corresponds to binary 0 and also to zero current tlow. An output potential level of +200 millivolts at the output terminals 40, on the other hand, is representative of binary l and corresponds to a current flow from the output junction 35 towards the output terminals 40. First, input signals corresponding to binary 0 are applied to each of the input terminals 41, 42, 43, such as represented by a potential level 72, FIG. 5, of +100 millivolts relative to ground. It is evident that to function as a nor gate, it is necessary that a signal representative of binary 1 or +200 millivolts be generated at the output terminals d in response to signals representative of binary 0 at the input terminals.

Referring now to FIG. 1, the potential source 54 generates a flow of current of the order of 2.7 milliamperes through the resistor 56 towards the junction 33; a tlow of current of the order of 2.7 miliiarnperes through the resistor S5 towards the junction 35'; and a flow of current of the order of 0.6 milliarnpere through the resistor 52 towards the junction 47. inasmuch as the potential level at each of the input terminals 4l, d2, d3 is at +100 millivolts, a substantial portion of the current of the order of 0.6 milliampere ilowing through resistor 52 initially flows through the backward diode d8 to the junction 3S. In addition, irrespective of the mode of conduction of tunnel diodes 30, 32, the clock pulse signal applied through capacitor ed periodically lowers the potential at junction 33, and, hence, lowers the potential drop from junction 33 to junction 34 to the extent that the voltage drop across both tunnel diodes 30, 32 is sufciently small to cause both tunnel diodes 30, 32 to revert to the unswitched mode of operation; i.e., current flow through each of the tunnel diodes 3:0 or 32 in this mode is less than the respective peak current, Ip. Under these circumstances, the tunnel diodes 30, 32 are both unswitched and the device is designated as having been cleared Subsequent to being cleared, the clock signal progressively increases the current llow through the tunnel diode 30 to the junction 35. Under these circumstances, the current llow through tunnel diode 32 is as follows:

wherein Irl-32 is the current (milliamperes) through tunnel diode 32; ITSO is the current (milliamperes) through tunnel diode 30; the current of 0.6 milliampere is the current through resistor 52; and the current of 2.7 milliamperes is the current through resistor 55. As is evident from Equation l, the current IT32 will reach a value of 5 milliamperes, the peak current, lp, of tunnel diode 32, prior to the current irl-30 reaching 2 milliamperes, the peak current, lp, of tunnel diode 30. Upon the current Irl-32 reaching 5 milliamperes, i.e., the peak current, lp, of tunnel diode 32, the diode 32 is switched whereby the potential drop .thereacross increases to approximately 350 millivolts, In that the backward diode 38 prevents the total potential drop from junction 33 to junction 34 from exceeding 400 millivolts, there is insuiiicient potential remaining to switch the remaining tunnel diode 30. The potential of junction 3S and, hence, the potential of output terminals i0 is determined by the potential drop across tunnel diode 32. n that the potential level of junction 34 is maintained at -150 millivolts relative to ground and the potential drop across tunnel diode 32 under these circumstances is 350 millivolts, the potential level available at junction 35 under these circumstances is necessarily +200 millivolts relative to ground. Immediately before and after being switched in this manner, the logic applied to the input terminals 41, 42, 43 has no effect on the potential level appearing at the output terminals 40. It is not until such time as the apparatus is set in the above-described manner that the logic applied to the input terminals has some eiect.

Next, assume that a potential level of -200 millivolts represented by level 74, FIG. 5, appears at one or more of the input terminals 4l, 42, 43. irrespective of the signals appearing at the input terminals di., 42, 43, the .apparatus is periodically cleared in the abovedescribed manner. Under this latter circumstance, however, the potential level of junction t7 is at -200 millivolts which is less than the potential level at junctions 35 or ground, thus diverting the current flow of 0.6 milliampere through resistor 52 from tunnel diode 32 y to the input terminals dl, d2 or 43. Current low now flowing through tunnel diode 32 is as follows:

As current liow through tunnel diode 30 increases, it is evident that .the peak current, Ip, of 2 milliamperes of tunnel diode 30 is reached prior to the peak current, Ip, of tunnel diode 32, which is 5 milliamperes. Thus, under the described circumstances, tunnel diode 30 is switched thereby preventing the switching of tunnel diode 32, as previously explained.

Fthe tunnel diode 32., in any event, determines the potential level at the output terminals 40. As can be seen from characteristic l0 of FIG. 6, the lpeak voltage, Vp, of a tunnel diode is somewhat less than millivolts and may be of the order of 50 millivolts. Thus, inasmuch as the junction 34 is maintained at -150 millivclts relative to ground by the power supply 37, a voltage drop of 50 millivolts across tunnel diode 32 maintains the output junction 35 together with the output terminals d0 at a potential level of -100 millivolts relative to ground.

Referring to PEG. 5, .there is shown the waveforml of clock signal 70 whereon the time C in the alternation is the instant the device is cleared and the time S in the alternation is the instant the device is set. ln addition, there is shown a waveform 76 which illustrates the voltage variations at the output terminals 40 for the binary H0 input and binary l inputs represented by voltages levels 72, 74, respectively. As previously explained, the potential levels 72, 7d need only be present at the time, S. Proceedingalong the waveforni 7o from the left, as viewed in the drawing, the output level proceeding from a point 77 to time C1 thereof corresponds to the circumstances where the tunnel diode'SQ; is in the switched position. At time C1, the sinusoidal clock signal represented by waveform 70 clears the device thus returning diode 32 to the unset mode of current conduction.v At this time, the potential level of waveform 76 decays from substantially +200 -rnil-livolts to +100 millivolts at point '78. The output potential level remains at this value until time S1, `at which instant the logic applied to the input terminals fil-i3 is such as to cause the tunnel diode 32 to be switched. This being the case, the potential level ot Waveform 76 progressively increases to approximately +200 millivolts throughout the remainder of the alternation and into the next successive a alternation. Subsequent to increasing to +200 millivolts, lthe clock signal causes a decrease until time C2 is reached, at which instant the device is again cleared. The potential level at the output again decreases until at a point 79 it decreases to -100 inillivolts. At the time, S2, the logic applied to the input is in this instance such as to require the tunnel diode 30 to be set, in which case the output potential level at output terminals d0 remain at substantially -l00 rnillivolts relative to ground. In the operation of the device of the present invention, it is intended to clear and set the device of FiG. l during either the a or alternation of the clock signal of wavetorrn 7i?. The exact instance at which clearing and setting occur may vary depending upon the amplitude of the clock signal applied to input terminal 60, the resistance of the resistor Se and the voltage applied thereto, the capacitance ofthe capacitor 6d, and the bias applied to backward diode 38 at the terminal opposite that ot junction 33 (shown connected to ground). It is generally desirable to clear and set the device during either the a or [3 alternation to provide logic during the next successive alternation of the clock Ysignal for one of the remaining devices. ln this respect, the setting of a subsequent device responsive to the waveform 76 would occur at times .S3 `and S4 prior to the device ot FIG. l being cleared at times C1, C2, respectively.

lvieasurcments have shown that the actual clearing or setting of the tunnel diodes 30, 32 of the device of l requires less than 0.35 nanosecond (109 seconds).

Referring now to Fl-G. 2, there is shown the device of FIG. 1 with appropriate modilications to ciect operation as a nor gate with a signal ol 200 millivolts representative of binary l a signal or +100 millivolts representative of binary and to transpose the clearing and switching times produced by the clock signal 70 180 in phase. In particular, the polarity of tunnel diodes 30, 32 is reversed from that described in FIG. 1 and the polarity of battery is reversed, ic., the positive terminal of battery' 5d is referenced to ground and the negative terminal connected to the resistors 52, 55 and 55 thereby to reverse the current ilow through these resistors. Also, the negative terminal of power supply 37 is referenced to ground and the positive terminal connected to the junction thereby to maintain this junction at +150 millivolts instead of at -150 millivolts as for the device of FIG. 1.

In operation, input signals of a potential level of +100 or 200 millivolts, representative or binary H0 or binary 1, respectively, are applied to the input terminals d1, 42. d3 in the same manner as described in connection with FIG. 1. Signals of potential levels of 200 millivolts or +100 millivolts, representative of binary l or "0, respectively, are generated at the output terminals As before, the clock signal '70 clears the device by decreasing the current dow through the tunnel diodes 30, 32 to the extent that current ow through each of the tunnel diodes reverts to the unswitched mode. Under these circumstances, current flows away from the junction 35 through the resistor 55, the backward diode 4S and resistor 52, and through the tunnel diode 30. On the other hand, current llows towards the junction 35 through tunnel diode 3?.. Assume lirst, that an input signal 0i a potential level of 100 millivolts, representative of binary 0 is applied to each of the input terminals di, d2 or As in the case of the device of FIG. 1, it is evident that tunnel diode 32 will switch, thereby producing a potential level of -200 millivolts, representative of binary "1 at the output terminals 40. Alternatively, when at least one of the input signals applied to input terminals LS1, 42 or i3 is of a potential level of 200 millivolts, representative of binary 1, the current flow through resistor 52 from junction 35 is diverted and will henceforth flow from the input terminal to which this input signal is applied. Thus, as before, as the clock signal increases the flow of current through the tunnel diodes 30, 32, the peak current, 2 milliamperes, of the tunnel diode 30 will be reached lirst whereby tunnel diode 30 is switched. In this case a potential level of +100 millivolts, representative of binary 0, is generated at the output terminals 40.

Referring now to FIG. 3 of the drawings, there is shown a preferred embodiment of an or gate in accordance with the present invention adapted to be responsive to and to generate a binary l gatinfr signal of positive polarity. in particular, tunnel diodes S0, 32 are serially connected from a junction E53 to a junction 3d and are poled in a manner to allow normal current how from junction 33 to junction Sil. A junction constitutes the common junction intermediate the tunnel diodes S0, 32. Also, as in the case of tunnel diodes 3u, 32, FIG. l, tunnel diode 80 is of a type having a peak current, lp, of 2 milliamperes, and tunnel diode 82 is ot a type having a peak current, ln, which is no less than the peak current diode 00 and is preferably of the order ot milliarnperes. in addition, as in the case of tunnel diodes 30, 57., tunnel diodes 80, S2 are presently available commercially as 1l`-l2969 and 1N294l, respectively. The junction is maintained at a. direct-current potential of the order or" +l50 millivolts relative to ground by means of a connection therefrom to a power supply 87 which is, in turn, referenced to ground. The junction 83, on the other hand, is returned to ground through a backward diode S8, which diode S8 1s poled in a direction to allow normal current llow from junction 83 towards ground. As in the case of the device of FIG. l, the `function of backward diode 3S is to prevent the potential dilterence between junctions 83 and 84 from exceeding 400 millivolts so that the tunnnel diodes 80, SZ cannot both be switched and, in addition, to prevent the tunnel diodes 80, 82 from penetrating into the region where the voltage thcreacross exceeds the valley voltage, Vv, where the recovery time of the respective diode is slow.

An output trom the device is provided by appropriate connections from the junction 85 intermediate the tunnel diodes 80, 82 to output terminals 90. The output signal produced at the output terminals is in the nature of a current or no current" corresponding, respectively, to +2 0 millivoits, representative of binary "1, and -100 millivolts, representative of binary 0. Inputs to the device are provided by input terminals 91, 92, 93. The input terminals 93., 92, 93 are connected through backward diodes 94, 9S, 96, respectively, to a common junction 97. Common junction 97 is, in turn, connected through a backward diode 93 to a junction 99 and, in addition, is returned to ground through a backward diode 100. The backward diodes 9d, 95, 96 are poled in a manner to allow normal current low towards the common junction 97, and the backward diodes 93, are poled in a manner to allow normal current how from ground towards the junction 99. As will hereinafter be explained in more detail, the purpose of backward diode 98 is to maintain the junction 97 positive with respect to junction 99 by from 100 to 150 millivolts. Next, a backward diode 101 is connected intermediate the junctions 85 and 99 and is poled to allow normal current flow from junction S5 towards junction 99.

Battery 10.?. having an intermediate terminal thereof referenced to ground provides a potential of the order of +5 volts at the positive terminal thereof and a potential of the order of -5 volts relative to ground at the negative terminal thereof. The positive terminal of battery i0?, is connected through a resistor 103 to junction S5, through a resistor 104 to junction 97, and the negative terminal thereof -is connected through a resistor 105 to the junction 99. The resistors 103, 104 have resistances of 1520 ohms and 5000 ohms, respectively, to provide substantially constant current llow of 3.3 milliamperes towards the junction. S5' and of 1.0 milliampere towards the junction 97. Resistor 105, on the other hand, has a resistance of 2630 ohms to provide a substantially constant current llow of 1.9 milliamperes away from the junction 99. irrespective of the input signals applied to the input terminals 91, 92 93, the current llow of 1.0 millinmpere toward the junction 97 flows through the backward diode 98 to the junction 99 to maintain the junction 97 from 100 to 150 millivolts positive relative to the junction 99 as previously specilied. lt is considered well within the scope of the teachings ol; the present invention to achieve this notential difference by other means such as a resistor and a capacitor connected in parallel between the junctions 97, 99, for example.

As in the case or the device of FIG. l, the device of FlG. 3 is adapted, but not restricted, to operate in response to the sinusoidal clock signal 70 which is applied to a terminal 108. Terminal l0?, is connected through a rc^istor dividing network to ground constituting resistors E09, 110, which resistors are serially connected in the order named from terminal 10S to ground. Resistor 5.09 has a resistance of the order of 500 ohms and resistor has a resistance or" the order of 56 ohms thereby to provide a voltage at the junction therebetween which is approximately 10% of the voltage applied to the clock input terminal l0" rhe voltage appearing at thc junction ,between resistors 109, H0 is coupled through a capacitor 111 to the junction 33 at one extremity of the tunnel diode 30 As before, the capacitor 111 has a capacitance of the order of microniicroiarads. Lastly, the clock curvilows therethrough from the junction S5.

rent through capacitor 11s is biased by a substantially constant current flow towards the junction SS of the order of 2.7 milliarnperes-` This curent flow is provided by a resistor 112 connected intermediate the positive terminal of battery ltlZ at the junction 83 and having a resistance of 1860 ohms,

in the operation of the device of HG. 3, the tunnel diodes 80, S2 arefperiodicaliy cleared as a direct result of the decrease in current therethrough produced by the clock signal 7i) in the same manner as for the device of FlG. 1. input signals representative of either binary 1 or binary are applied to the input terminals 9i, 92, 93. Binary 0 is detined as a potential level of 100 millivolts and binary l as a potential level of 20G Inillivolts. In the event that all of the input signals applied to the input terminals 91, 92, 93 are representative ot binary 0 and, as such, are of a potential level of 100 millivolts, substantially no current liows through the backward diodes d, 95, 96, The reason for this is that current ilow through the backward diode 1d@ maintains the potential of junction 97 at a potential of +100 millivolts relative to ground whereby thepotential across the backward diodes 9d, 9S, 9d is substantially zero. At the junction 97, the current flow through backward diode 145i) combines with the current flow oi 1 milliainpere through resistor 104 and lows through the backward diode 9S thereby to maintain the potential of junction 99 at +20() rnillivolts relative to ground. ln that the potential of junction 8S together with that of the output terminals 9rd is at -100 milivots, a current of the order of 0.6 milliampere tlows through the backward diode 161 into the junction 9i? to make up the 1.9 rnilliarnperes flowing out of junction 99 through the resistor 195. Under these circumstances, only a portion of the 3.3 milliarnperes flowing through the resistor lofi into junction 8S iiows through the tunnel diode 2. More particularly, 0.6 milliarnpere of this current is diverted through the backward diode 162i leaving 2.7 milliamperes owing through the tunnel diode 82. Thus, as the clock signal 7o increases the current flow through the tunnel diode Si?, it is evident that the peak current, lp, of 2 milliamperes of tunnel diode 86 will be exceeded while the current ilow through the tunnel diode S2 is less than its peak current, lp, of 5 milliampcres. Accordingly, when signals representative of binary "0 are applied 'to the input terminals gl, d2, 93, the tunnel diode Eil will switch, thus producing a potential at the junction 85' in the output terminals till of G millivolts. This latter potential of 10G millivolts is determined by the voltage drop across the tunnel diode 32 which, under these circumstances, is oi the order of 50 millivolts. Thus, inasmuch as the junction 8d is maintained at +15() millivolts relative to ground, the potential at the output terminals 9d will be at 100 millivolts and representative oi binary {(0.1}

Consider now the circumstances when one of the input signals applied to input terminals 91, 92 or 91' is of a potential level oi +200 millivolts, i.e.,v representative ci binary L Current will now flow through the backward diode 9d, 95 or Qd into the junction i increasing the potential thereof to approximately +100 inillivolts relative to ground, thereby backbiasing the backward diode 169. This current combines with the 1 iuilliampere flowing through resistor 194 and flows through the backward diode 58 thereby to produce a potential level ot zero volts at the junction 99. ln that the potential level subsequent to being cleared at the output terminals 9o is 106 millivolts, the backward diode lill between junctions gt and 8S is now backbiased whereby no current Under these circumstances, an increase in current through the tunnel diode Si? produced by the clock'signal 'itl combines with the 3.3 milliarnperes tlowing into junction 3S through resistor 103 and iiows through the tunnel diode 82. rlhe current through tunnel diode d2 thus reached 5 rnilliarnperes, the peak current thereof, before the current riowing through tunnel diode d@ reaches 2 milliarnperes. Thus, if one or more of the signals applied to the input terminals 91, 92 or 93 is representative of binary 1, the tunnel diode 82 will switch thus producing a voltage drop of 350 rnilivolts thereacross and a voltage of +200 millivolts at the junction 35 and the output terminals iid.

Referring to FlG. 4, there is shown an or gate in accordance with the present inventionadapted to operate in response to input signals of a potential level of +200 millivolts representative of binary l and having a potential level of +10() millivolts representative of binary 0., Output signals of a potential level of rnillivolts, representative or' binary 1, and of potential level of +100 millivolts, representative of binary 0, are produced at output terminals 9i). in general, the device of FIG. 4 is the same as that of FIG, 3 with the exception that the backward diodes 35, 9d, 9:3, 96, 9S, ilil and 161, together with the tunnel diodes 8l?, S2, are poled in the opposite direction and the polarity of the power supply 87 of battery ltl is reversed. Under these circumstances, clearing and switching is transposed 186 along the clock signal "itl, FIG. 5. The operation of the remainder of the circuit is similar to that of FlG. 3 with the exception that all currents are reversed.

What is claimed is:

1. A digital computer device comprising:

(a) rst and second tunnel diodes having first and second peak currents, respectively, serially connected in the order namedy from a iirst junction to an output junction and from said output junction to a second junction, said second peak current being greater than said irst peak current and said irst and second tunnel diodes being poled to allow normal current iiow therethrough in a common direction from said first to said second junction;

(b) means connected to said second junction for rnaintaining said second junction at a iirst substantially iixed potential relative to a reference potential;

(c) means connected to said iirst junction for maintaining the potential ditierence between said first and second junctions at values less than the least sum of the valley voltage ot one of said tunnel diodes and the peak voltage of the other tunnel diode;

(d) means connected to said output junction for maintaining a predetermined current flow through said second tunnel diode;

(e) means coupled to said rst junction for periodically decreasing and increasing the current how through said first and second tunnel diodes whereby both of said tunnel diodes periodically revert to the unswitched mode of current conduction in response to said periodic decreases in current flow thereby to produce a substantially constant rst potential level at said output junction; and v (f) means responsive to no less than one bi-level input signal for changing the current iiow through at least one of said tunnel diodes thereby to selectively switch one or the other ot said iirst and second tunnel diodes during each periodic increase in current iiow therethrough as determined by a preselected combination of potential levels of said no less than one input signal whereby the switching of said second tunnel diode generates a second potential level at said output junction.

2. The digital computer device as deiined in claim 1 wherein said means connected to said iirst junction for maintaining the potential diference between said iirst and second junctions at values less than the least sum of the valley voltage of one of said tunnel diodes and the peak voltage of the other tunnel diode includes a backward diode connected from said iirst junction to a third junction maintained at a second substantially tixed potential relative to said reference potential, said backward diode being poled to allow normal current tiow energetic ii therethrough in the saine direction as said common direction with respect to said first junction.

3. The digital computer device as defined in claim l wherein said means coupled to said first junction for periodically decreasing and increasing the current iow through said rst and second tunnel diodes constitutes a single phase source of sinusoidal potential and a directcurrent source of biasing current connected to said first junction.

4. A digital computer device comprising:

(a) first and second tunnel diodes having rst and second peak currents, respectively, serially connected in the other named from a first junction to an output junction and from said output junction to a second junction, said first and second tunnel diodes being polcd to allow normal current fiow therethrough from said rst to said second junction and said second peak current being no iess than said first peak current;

(b) means connected to said second junction for maintaining said second junction at a substantially iixed negative potential relative to a reference potential;

(c) a backward diode connected from said rst junction to a third junction maintained at said reference potential, said backward diode being poled to allow normal current fiow from said first to said third junction;

(d) means connected to said output junction for rnaintaining a predetermined current ilow through said second tunnel diode;

(e) means including a source of single-phase sinusoidal potential coupled to said rust junction for periodically decreasing and increasing the current flow through said first and second tunnel diodes whereby both of said tunnel diodes periodically revert to the unswitched mode of current conduction in r spense to said periodic decreases in current fiow thereby to produce a substantially constant first potential level at said output junction; and

(j) means responsive to a plurality of bi-level input signals representative of binary i or binary "0 for not increasing said current dow through said second tunnel diode when all of said plurality of bi-level input signals are representative of binary "0 and for increasing said current flow through said second funnel diode when at least one of said plurality of bi-level input signals is representative of binary 1" thereby to switch said second tunnel diode during each periodic increase in current iiow therethrough when no less than one of said plurality of input signals is representative of binary "1 whereby the ivitching of said second tunnel diode generates a second potential level at said output junction.

5. A digital computer device comprising:

(a) first and second tunnel diodes having first and second peak currents, respectively, serially connected in the order named from a iirst junction to an output junction and from said output junction to a second junction, said first and second tunnel diodes being poled to allow normal current flow therethrough from said first to said second junction and said second peak current being no less than said first peak current;

(b) nieans connected to said second junction for maintaining said second junction at a substantially fixed negative potential relative to a reference potent (c) a backward diode connected from said Vfirst junction to a third junction maintained at said reference potential, said backward diode being poled to ailow normal current flow from said first to said third junction;

(d) means connected to said output junction for maintaining a predetermined current flow through said second tunnel diode;

(e) means including source of single-phase sinusoidal potential coupied to said first junction for periodically decreasing and increasing the current flow through said first and second tunnel diodes whereby both of said tunnel diodes periodically revert to the unswitched mode of current conduction in response to said periodic decreases in current flow thereby to produce a substantially constant first potential level at said output junction; and

(f) means responsive to a plurality of bi-level input signals, representative of binary "l or binary "0 for diverting at least a portion of the current flow through said second tunnel diode only when no less than one of said plurality of bi-level input signals is representative of binary "1 thereby to switch said second tunnel diode during cach periodic increase in current iow therethrough when no portion of the current flow through said second tunnel diode is diverted or to switch said first tunnel diode during each periodic increase in current flow therethrough when at least a portion of the current flow through said second tunnel diode is diverted, Vthe switching of said second tunnel diode generating a second potential level at said output junction.

6. A digital computer device comprising:

(a) irst and second tunnel diodes having first and second peak currents, respectively, serially connected in the order narned from a first junction to an output junction and from said output junction to a second junction, said first and second tunnel diodes being poled to allow normal current flow therethrough from said second to said first junction and said second peak current being no less than said first peak current;

(b) means connected to said second junction for maintaining said second junction at a substantially fixed positive potential relative to a reference potential;

(c) a backward diode connected from said rst junction to a third junction maintained at said reference potential, said backward diode being polcd to allow normal current fiow from said third to said first junction;

(d) means connected fo said output junction for maintaining a predetermined current flow through said second tunnel diode;

(e) means including a source of single-phase sinusoidal potential coupled to said first junction for periodically decreasing and increasing the current ow through said first and second tunnel diodes whereby both of said tunnel diodes periodically revert to the unswitched mode of current conduction in response to said periodic decreases in current flow thereby to produce a substantially constant first potential level at said output junction; and

(f) means responsive to a plurality of bi-level input signals, representative of binary "1 or binary "0 for diverting at least a portion of the current flow through said second tunnel diode only when no less than one of said plurality of bi-levcl input signals is representative of binary "1 thereby to switch said second tunnel diode during each periodic increase in current ffow therethrough when no portion of the current iiow through said second tunnel diode is diverted or to switch said first tunnel diode during each periodic increase in current flow therethrough when at least a portion of the current flow through said second tunnel diode is diverted, the switching of said second tunnel diode generating a second potential level at said output junction.

7. A digital computer device comprising:

(a) first and second tunnei diodes having rst and second peak currents, respectively, serially connected in the order named from a rst junction to an output junction and from said output junction to a second junction, said first and second tunnel diodes Vbeing poled to allow normal current ilow therethrough from said second to said rst junction and said second peak current being no less than said rst peak current;

(b) means connected to said second junction for maintaining said second junction at a substantially xed positive potential relative to a reference potential;

(c) a backward diode connected from said first junction to a third junction maintained at said reference potential, said backward diode being poled to allow normal current flow from said third to said rst junction;

(d) means connected to said output junction for mainraining a predetermined current flow through said second tunnel diode;

(e) means including a source of single-phase sinusoidal potential coupled to said rst junction for periodically decreasing and increasing the current ow through said first and second tunnel diodes whereby both of said tunnel diodes periodically revert to the unswitched mode of current conduction in response to said periodic decreases in current flow thereby to produce a substantially constant first potential level at said output junction; and

(f) means responsive to a plurality of bi-level input signals representative of binary l or binary "0 for not increasing said plurality of bi-level input signals are representative of binary "0 and for increasing said current flow through said second tunnel diode when at least one of said plurality of bi-level input signals is representative of binary l thereby to switch said second tunnel diode during each periodic increase in current ow therethrough when no less than one of said plurality of input signals is representative of binary 1 whereby the switching of said second tunnel diode generates a second potential level at said output junction.

References Cited in the tile of this patent G.E. Tunnel Diode Manual, Mar. 20, 1961 (pages 58 to 60 relied on).

Hoffman Electronics Corporation Advertising Brochure,

1960 (pages 8, 9, 40A relied on).

Proceedings of the Eastern Joint Computer Conference,

20 1959 (pages 43 and 44 relied on).

to 3 relied on).

UNITED STATES PATENT OFFICE CERTIFICATE 0E CORRECTION Patent No 3, l5584 November 3Y 1964 O D Parham It is hereby certified that error appears in the above numbered patent requiring correction and that the said Letters Patentshould read as corrected below.

Column 2, line 52V strike out Y"valley voltage" VVY of the tunnel diode and occursq forY and insert instead --'I valley voltage again produce an increase in current flowa column l1, line 139 for "other read order Signed and sealed this 6th day of April 1965,

(SEAL) Attest:

ERNEST W. SWIDER EDWARD J. BRENNER Aitcsting Officer Commissioner of Patents 

1. A DIGITAL COMPUTER DEVICE COMPRISING: (A) FIRST AND SECOND TUNNEL DIODES HAVING FIRST AND SECOND PEAK CURRENTS, RESPECTIVELY, SERIALLY CONNECTED IN THE ORDER NAMED FROM A FIRST JUNCTION TO AN OUTPUT JUNCTION AND FROM SAID OUTPUT JUNCTION TO A SECOND JUNCTION, SAID SECOND PEAK CURRENT BEING GREATER THAN SAID FIRST PEAK CURRENT AND SAID FIRST AND SECOND TUNNEL DIODES BEING POLED TO ALLOW NORMAL CURRENT FLOW THERETHROUGH IN A COMMON DIRECTION FROM SAID FIRST TO SAID SECOND JUNCTION; (B) MEANS CONNECTED TO SAID SECOND JUNCTION FOR MAINTAINING SAID SECOND JUNCTION AT A FIRST SUBSTANTIALLY FIXED POTENTIAL RELATIVE TO A REFERENCE POTENTIAL; (C) MEANS CONNECTED TO SAID FIRST JUNCTION FOR MAINTAINING THE POTENTIAL DIFFERENCE BETWEEN SAID FIRST AND SECOND JUNCTIONS AT VALUES LESS THAN THE LEAST SUM OF THE VALLEY VOLTAGE OF ONE OF SAID TUNNEL DIODES AND THE PEAK VOLTAGE OF THE OTHER TUNNEL DIODE; (D) MEANS CONNECTED TO SAID OUTPUT JUNCTION FOR MAINTAINING A PREDETERMINED CURRENT FLOW THROUGH SAID SECOND TUNNEL DIODE; (E) MEANS COUPLED TO SAID FIRST JUNCTION FOR PERIODICALLY DECREASING AND INCREASING THE CURRENT FLOW THROUGH SAID FIRST AND SECOND TUNNEL DIODES WHEREBY BOTH OF 